Many efforts have been directed at producing complementary PNP and NPN transistor pairs on a common monolithic semiconductor substrate. Generally, two problems have been encountered in producing complementary transistor pairs. Firstly, because of the lesser mobility of holes relative to electrons, PNP transistor characteristics are inherently inferior to those of NPN transistors. PNP transistors usually have a beta (current gain) of no higher than about 10 and a cutoff frequency of no higher than about 500 MHz, whereas NPN transistors generally have a beta in excess of about 80 and a cutoff frequency in excess of about 3.5 GHz.
Although techniques have been available for tailoring impurity profiles in the respective emitter, base and collector regions of complementary transistors, it has usually been necessary to degrade the performance of the NPN transistor to match the performance characteristics of the PNP transistor. Secondly, it is necessary to provide a doped barrier around one of the pairs of complementary transistors. In the usual case of using a P-doped semiconductor substrate, an N-doped barrier must be formed around the PNP transistor. Many problems have been encountered in providing such doped barrier due to the tendency of the barrier surrounded transistor to regard the barrier as a further PN junction and to create a secondary transistor effect.